With the development of integrated circuit (IC) technology, the size of the semiconductor devices has become smaller and smaller. In order to lower the parasitic capacitance of the gates of MOS transistors and increase the device speed, a stacked layer structure with high dielectric constant (high-K) gate dielectric layer and a metal gate (may be referred as an HKMG structure) have been introduced into the MOS transistors. Further, in order to prevent the metal of the HKMG structure from affecting other structures of the MOS transistor, the HKMG structure may be formed by a gate-last process.
FIGS. 1˜3 illustrate semiconductor structures corresponding to certain stages of an existing gate last process for forming the high-K metal gate of a MOS transistor.
As shown in FIG. 1, a semiconductor substrate 10 is provided, and a poly silicon dummy gate structure 20 and an interlayer dielectric layer 30 are sequentially formed on the semiconductor substrate 10. The poly silicon dummy gate structure 20 includes a high-K gate dielectric layer 21 on the surface of the semiconductor substrate 10, a functional high-K gate dielectric protection layer 22 on the high-K gate dielectric layer 21, and a poly silicon dummy gate 23 on the functional high-K gate dielectric protection layer 22. The surface of the interlayer dielectric layer 30 may level with the surface of the poly silicon dummy gate structure 20. Further, as shown in FIG. 2, the silicon dummy gate 23 is removed, and a trench 25 is formed. The bottom of the trench 25 exposes the surface of the functional high-K gate dielectric protection layer 22. Further, as shown in FIG. 3, a metal gate 26 is formed in the trench 25.
However, such a MOS transistor with the HKMG structure 20 may have a relatively high leakage current. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.